1. Field of the Invention
The present invention relates to a semiconductor device fabrication and more particularly, to a fabrication method of a semiconductor device, which is capable of effective gettering treatment during a fabrication process sequence with respect to miniaturized and integrated semiconductor devices using upsized semiconductor substrates or wafers.
2. Description of the Prior Art
In recent years, miniaturization and integration of semiconductor elements and upsizing of semiconductor substrates or wafers have been progressing more and more in the field of semiconductor devices. According to this tendency, the process temperature has been required to be lowered. Therefore, the need for improvement in gettering treatment has been becoming stronger.
Although the conventional Denuded-Zone Intrinsic Gettering (DZIG) treatment was effective for conventional high-temperature fabrication processes, it has been becoming unsuitable to the recent fabrication processes which are carried out at temperatures lower than 1000.degree. C. This is because a desired gettering or trapping site is difficult to be formed at such the low temperatures.
Specifically, to form a controlled defect-free zone (i.e., "denuded zone") serving as a gettering or trapping site in the interior of a semiconductor wafer using the DZIG treatment, the wafer is essential to be subjected to high-temperature thermal processes performed at temperatures ranging from typically 1000.degree. C. to 1200.degree. C.
A known solution to the above need for gettering treatment improvement is the Polysilicon-Back-Sealing (PBS) method. This PBS method was been disclosed, for example, in the Japanese Non-Examined Patent Publication No. 5-275436 published in October 1993. In this method, a polysilicon film serving as a gettering site is deposited on the back side of a single-crystal silicon wafer or substrate, thereby forming a PBS wafer. Then, the PBS wafer is subjected to heat treatment under specific conditions.
The PBS method is a typical one of extrinsic gettering treatments.
FIGS. 1 and 2 illustrate the time-dependent temperature change in the gettering treatments using the PBS method disclosed in the Japanese Non-Examined Patent Publication No. 5-275436. In these Figures, the axis of abscissa represents the time in arbitrary unit.
In a first one of the conventional gettering treatments using the PBS method, as shown in FIG. 1, a PBS silicon wafer is heated in an electric furnace from a temperature of approximately 800.degree. C. up to approximately 900.degree. C. This heating process is carried out in the same way as that of popular electric-furnace heat treatments. Next, the PBS wafer is held at approximately 900.degree. C. for a specific period. Then, it is gradually cooled to a temperature of 400 to 700.degree. C. at a cooling rate of 3.degree. C./min.
In a second one of the conventional gettering treatments using the PBS method, as shown in FIG. 2, a PBS silicon wafer is heated in an electric furnace from a temperature of approximately 800.degree. C. up to approximately 900.degree. C. This heating process is carried out in the same way as that of popular electric-furnace heat treatments. Next, the PBS wafer is held at approximately 900.degree. C. for a specific period. Then, it is cooled to a temperature in the range of 400 to 700.degree. C. and held at this temperature for a specific period.
In these two conventional gettering treatments, metallic impurities such as heavy metals (e.g., Fe) existing in the interior of the PBS wafer are gettered or trapped in the polysilicon film deposited on the back side of the wafer during the gradual cooling period from a temperature of 900.degree. C. to another temperature of 400 to 700.degree. C., or the holding period at the temperature of 400 to 700.degree. C., respectively.
With these conventional gettering treatments, however, the following problems will occur if miniaturization and integration of semiconductor elements and upsizing of semiconductor substrates or wafers further progress.
First, the wafer upsizing increases the thickness of a silicon wafer itself. For example, a silicon wafer with a diameter of 6 inches needs to have a thickness of approximately 0.675 mm. In this case, to remove not only metallic impurities such as ferrum (Fe) which are inherent in the silicon wafer but also those which are doped into the wafer during subsequent fabrication processes using the PBS method, the latter impurities need to diffuse from the main surface of the wafer to the back side thereof.
For example, it is required for the 6-inch silicon wafer to be held at a temperature of approximately 900.degree. C. for such a long period as 10 to 20 minutes. This holding period will be longer with the increasing diameter of the wafer.
Accordingly, the gradual cooling step from the temperature of approximately 900.degree. C. to 400 to 700.degree. C. at the cooling rate of -3.degree. C./min and the holding step at the temperature of 400 to 700.degree. C. for the specific period, both of which are disclosed in the Japanese Non-Examined Patent Publication No. 5-275436, are insufficient for the metallic impurities to be gettered. For example, the 6-inch wafer is essential to be held at 900.degree. C. for a specific period.
Second, the progressing miniaturization and integration decreases the depth (X.sub.j) of p-n junctions of heavily-doped diffusion regions formed at the main surface of a silicon wafer. For example, the depth (X.sub.j) needs to be as small as approximately 0.1 .mu.m for Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) fabricated at a design rule of 0.25 .mu.m.
With p.sup.+ -type diffusion regions heavily doped with boron (B) and n.sup.+ -type diffusion regions heavily doped with phosphorus (P), both of which have a doping concentration of 10.sup.19 to 10.sup.20 atoms/cm.sup.3, it is known that the dopant atoms will diffuse at an increased diffusion rate. This phenomenon is termed the "enhanced diffusion".
Therefore, for example, with a p-channel MOSFET having p.sup.+ -type diffusion regions heavily doped with boron, which has the p-n junction depth (X.sub.j) of approximately 0.1 .mu.m and which is fabricated through ion-implantation of boron difluoride (BF.sub.2) with a dose of 5.times.10.sup.15 atoms/cm.sup.2 at an acceleration energy of 30 keV and rapid thermal annealing (RTA) at a temperature of 950.degree. C. for 10 seconds, there is a problem explained below.
Specifically, if this MOSFET is subjected to a gettering treatment at 900.degree. C. for 10 minutes, operation characteristics of the MOSFET tend to degrade. For example, the "short channel effect" tends to occur. This is because the heat treatment at 900.degree. C. for 10 minutes increases the p-n junction depth (X.sub.j) by approximately 0.05 .mu.m.
The same degradation in operation characteristics takes place in the other MOSFETs having n.sup.+ -type diffusion regions, which are heavily doped with phosphorus.
The same degradation in operation characteristics takes place in npn-type bipolar transistors, also. In the bipolar transistors, leakage current increase between a p.sup.+ -type graft base region and an n.sup.+ -type emitter region tends to occur.
As described above, the conventional gettering treatments are unable to cope with the progressing miniaturization and integration of semiconductor elements and upsizing of semiconductor substrates or wafers.
Moreover, with a MOSFET having the self-aligned silicide (SALICIDE) structure where titanium suicide (TiSi.sub.2) films are respectively deposited on the top surfaces of heavily-doped diffusion regions (i.e., source/drain regions) and a gate electrode in self-alignment, aggregation of TiSi.sub.2 tends to occur if this MOSFET is subjected to heat treatment at a temperature of 850.degree. C. or higher after the formation of the SALICIDE structure. This aggregation causes a problem of increase in sheet resistance of the gate electrode.
This problem is more distinctive in the top surface of the gate electrode than the source/drain regions.
Consequently, the above-described conventional gettering treatments are not suitable to the MOSFETs having the SALICIDE structure.